1. Field of the Invention
The present invention relates generally to semiconductor devices and more particularly to metal-oxide-semiconductor devices having shallow source and drain regions, and a method of manufacturing thereof. The present invention is particularly utilizable in the field of PSD (Poly-silicon Source and Drain) structure of semiconductor devices.
2. Description of the Prior Art
Recently, semiconductor devices have been developed for the purposes of enhancing integration scales of semiconductor devices and improving reliability thereof according to an increasing demand for higher techniques. Those purposes are in some aspect contradictory. Enhancement of integration scales of semiconductor devices might cause lowering of reliability thereof to the contrary. Consequently, techniques which can accomplish both of those purposes will be very useful.
One of typical semiconductor devices is a MOS (metal oxide semiconductor) transistor. Technical developments have been also promoted in such MOS transistors for the purposes of fine reduction of device structures and improvement of reliability. An example of a fine structure of a MOS transistor is indicated in Japanese Patent Laying-Open No. 16573/1986. This MOS transistor, having a so-called PSD structure will be described in the following.
Referring first to FIG. 4G, the structure of the MOS transistor will be described. Source and drain regions 6 and 7 are formed to be spaced from each other on a surface region of a silicon substrate 1. Electrode layers 5 of polysilicon are formed on surfaces of the source and drain regions 6 and 7. Those electrode layers 5 extend over upper surfaces of an oxide film 2 for device isolation. A surface region of the silicon substrate 1 placed between the source and drain regions 6 and 7 is called a channel region 4. A gate electrode layer 14 of polysilicon is formed on the channel region 4 through a gate oxide film 3. The gate electrode layer 14 is insulated between the respective electrode layers 5 through an insulating film 8. Some portions of the gate electrode 14 extend over upper surfaces of the electrode layers 5 through the insulating film 8. The outgoing electrode layers 5 from the source and drain regions 6 and 7 are connected with a source electrode connection layer 15 and a drain electrode connection layer 16 located above the isolation oxide film 2.
This prior art transistor has the below described features from a viewpoint of fine reduction of the structure.
(1) The gate electrode layer 14 has a form in which a gate electrode width in a lower portion and that in an upper portion are different. The electrode width in the lower portion of the gate electrode layer 14 is shorter and a channel length of the MOS transistor defined by this width is reduced. The electrode width of the upper portion of the gate electrode layer 14 is larger and this serves to suppress reduction of a sectional area of the gate electrode layer 14. Suppression of the reduction of the sectional area of the gate electrode layer 14 makes it possible to prevent increase of a connection resistance of the gate electrode layer 14.
(2) The source region 6 and the drain region 7 are brought into contact with the electrode connection layers 15 and 16 through the electrode layers 5 over the isolation oxide film 2. In consequence, it is not necessary to provide space for direct contact between the source and drain regions 6 and 7 and the electrode connections 15 and 16. As a result, a diffusion area of impurity in the source and drain regions 6 and 7 can be reduced.
Next, a method of manufacturing the above described MOS transistor will be described with reference to FIGS. 4A to 4G.
First, as shown in FIGS. 4A, an isolation oxide film for device isolation is formed on a surface of a silicon substrate 1 by using a thermal oxidation process.
Then, as shown in FIG. 4B, a polycrystal silicon film containing impurity of a conductivity type opposite to that of the silicon substrate 1 is formed thereon.
Further, as shown in FIG. 4C, a silicon oxide film 8 is deposited over the polycrystal silicon film 5.
After that, as shown in FIG. 4D, the silicon oxide film 8 and the polycrystal silicon film 5 are selectively removed by using a photolithographic process and a plasma dry etching process, whereby an opening 9 is formed.
Then, as shown in FIG. 4E, heat treatment is applied in an oxidizing atmosphere, whereby a gate oxide film 3 is formed on the surface of the silicon substrate 1 exposed in the opening 9 and at the same time sidewalls of the polycrystal silicon film 5 facing the opening 9 are oxidized to form a sidewall oxide film 10. Then, heat treatment is applied in a nitrifying atmosphere, whereby the impurity contained in the polycrystal silicon film 5 is diffused into the silicon substrate 1 to form a source region 6 and a drain region 7.
Further, as shown in FIG. 4F, the silicon oxide film 8 is selectively removed to provide contact holes 11 and 12 which allow contact between the polycrystal silicon film 5 for the source and drain electrodes and connection layers.
Further, as shown in FIG. 4G, a polycrystal silicon film is deposited over the whole surface and patterned in a desired form. As a result, a gate electrode layer 14 and connection layers 15 and 16 for the source and drain electrodes are formed.
Thus, in this prior art example, the source and drain regions 6 and 7 are formed on the surface of the silicon substrate 1 by thermal diffusion of the impurity contained in the polycrystal silicon film 5.
Usually, in a MOS transistor, the device structure is finely reduced according to a proportional reduction ratio so as not to deteriorate characteristics of the transistor. For this purpose, it is necessary to form source and drain regions with an impurity diffusion depth as shallow as possible. In the conventional method of manufacturing a MOS transistor as described above, the source and drain regions are formed by thermal diffusion of the impurity from the polycrystal silicon film. Thus, the impurity contained in the polycrystal silicon film is easily diffused into the silicon substrate 1 since the polycrystal silicon film is exposed to high temperatures in various manufacturing steps for the transistor. For example, in the step shown in FIG. 4C, when the silicon oxide film 8 is deposited by a CVD method, the impurity contained in the polycrystal silicon film 5 is diffused into the silicon substrate 1 as this film is exposed to a high temperature of about 850.degree. C. In this case, impurity of a conductivity type opposite to that of the silicon substrate 1 is diffused into a region to be a channel region on the surface of the silicon substrate 1. If the concentration of the thus diffused impurity exceeds a predetermined value, the transistor manufactured does not operate.
In addition, in the step shown in FIG. 4E, the impurity contained in the polycrystal silicon film 5 is easily diffused into the silicon substrate 1 also by thermal oxidation for forming the gate oxide film 3. Further, a thermal diffusion process for forming the source and drain regions 6 and 7 is applied thereafter.
Thus, the source and drain regions 6 and 7 are formed by several thermal processes in the manufacturing steps of the MOS transistor. Therefore, the impurity is easily diffused into the silicon substrate 1 and it is difficult to control the diffusion to form a shallow diffusion depth. In addition, the source and drain regions subjected to those thermal processes extend also along the flat surface of the semiconductor substrate, causing a decrease in an effective channel width of the transistor. As a result, the so-called short channel effect occurs conspicuously, causing deterioration of the characteristics of the transistor.
The well-known DDD structure is adopted to reduce the short channel effect by forming source and drain regions with double diffused structure including a lower impurity concentration layer underlying and surrounding a higher impurity concentration region. This DDD structure reduces the short channel effect because the graded impurity density profile of the structure reduces the size of the depletion field in the channel region of the device. However, no means for applying such a DDD structure to a MOS transistor having a PSD structure has been realized.